Module Specification |
The information contained in this module specification was correct at the time of publication but may be subject to change, either during the session because of unforeseen circumstances, or following review of the module at the end of the session. Queries about the module should be directed to the member of staff with responsibility for the module. |
Title | Integrated Circuits - Concepts and Design | ||
Code | ELEC472 | ||
Coordinator |
Dr M Raja Electrical Engineering and Electronics M.Raja@liverpool.ac.uk |
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Year | CATS Level | Semester | CATS Value |
Session 2023-24 | Level 7 FHEQ | Whole Session | 15 |
Aims |
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To understand the reasons for the predominance and importance of silicon-based microelectronics to the semiconductor industry. To understand how materials, devices and circuit issues are inter-related and exploited to make the microchips that underpin the information age. To prepare students for entering the Silicon semiconductor industry. |
Pre-requisites before taking this module (other modules and/or general educational/academic requirements): |
ELEC212 CMOS Integrated Circuits |
Co-requisite modules: |
Learning Outcomes |
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(LO1) Appreciation of MOS based integrated circuit design philosophy: power, speed, yield, packing density considerations and of design trade-offs associated with materials, device and circuit limitations. |
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(LO2) Knowledge of how to analyse and design simple MOS logic gates and amplifier stages. |
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(LO3) Appreciation of historical and future development of silicon based integrated circuit technology. |
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(LO4) Knowledge of silicon integrated circuit technology. |
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(LO5) Appreciation of some IC design issues. |
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(LO6) Ability to use simulation tool (i.e. Multisim) to design, layout and test by simulation digital circuit cells. |
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(S1) On successful completion of the module, students should be able to show experience and enhancement of the following key skills: Independent learning. Problem solving and design skills. |
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(S2) On successful completion of the module, students will have skill to utilise software package such as Multisim, in the design and simulation of circuit designs. |
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(S3) On successful completion of the module, students should be able to demonstrate the ability to apply knowledge of the module concepts on simulation package such as Multisim in the design and testing of digital/analogue circuits. |
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(S4) On successful completion of the module the student is expected to have: Appreciation of MOS based integrated circuit design philosophy: power, speed, yield, packing density considerations and of design trade-offs associated with materials, device and circuit limitations. Knowledge of how to analyse and design simple MOS logic gates and amplifier stages. Appreciation of historical and future development of silicon based integrated circuit technology.Knowledge of silicon integrated circuit technology. Appreciation of some IC design issues. |
Syllabus |
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1. The MOS transistor Revision of MOST equations, subthreshold operation and substrate bias effects, device design considerations, substrate current and reliability, device capacitance, the SPICE model, Moore's Law. 2. Evolution of MOS logic families with circuit analysis Resistor, saturated and unsaturated MOST load, depletion load (nMOS) technologies: basic inverter operation, advantages and disadvantages of each. 3. The CMOS Inverter basic operation, transfer characteristic, transient response, latch-up and its suppression. 4. CMOS circuits NAND, NOR, Realisation of more complex combinational gates: Composite (AOI), MOS scaling, low voltage/low power issues and circuits. 5. Dynamic circuits nMOS and CMOS transfer gates, shift register, pre-charge concept and domino logic, design issues: charge sharing, charge coupling and delay hazards, clocked combinational logic, PLA. 6. Semiconductor fabrication processing Oxidation, doping, lithograph y, yield, CMOS process flow, design rules, transistor parasitic, capacitance, latch-up and its suppression. 7. Analogue CMOS circuits Circuit building blocks, Common source amplifiers with active loads; differential amplifier, micro-power amplifiers, temperature effects. |
Teaching and Learning Strategies |
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Due to Covid-19, one or more of the following delivery methods will be implemented based on the current local conditions and the situation of registered students. It is anticipated that both a) & b) will be in operation for semester 1. (a) Hybrid delivery, with social distancing on Campus Teaching Method 2 - Synchronous face to face tutorials Teaching Method 3 - Campus based Laboratory Work Tutorials (b ) Fully online delivery and assessment Teaching Method 1 - On-line asynchronous lectures Teaching Method 2 - On-line synchronous tutorials Teaching Method 3 - on-line Laboratory Work Tutorials (c) Standard on-campus delivery with minimal social distancing Teaching Method 2 - Tutorial Teaching Method 3 - Laboratory Work |
Teaching Schedule |
Lectures | Seminars | Tutorials | Lab Practicals | Fieldwork Placement | Other | TOTAL | |
Study Hours |
16 |
72 |
6 |
94 | |||
Timetable (if known) | |||||||
Private Study | 56 | ||||||
TOTAL HOURS | 150 |
Assessment |
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EXAM | Duration | Timing (Semester) |
% of final mark |
Resit/resubmission opportunity |
Penalty for late submission |
Notes |
Standard resit opportunity is available. Standard UoL penalty applies for late submission. Assessment Schedule (When): January (Semester 1) | 2 | 60 | ||||
CONTINUOUS | Duration | Timing (Semester) |
% of final mark |
Resit/resubmission opportunity |
Penalty for late submission |
Notes |
Assessment 3 Resit opportunity for this component is available via another coursework. Standard UoL penalty applies for late submission. Assessment Schedule (When): Semester 2, Approx. Week 1 | 0 | 15 | ||||
Assessment 2 Resit opportunity for this component is available via another coursework. Standard UoL penalty applies for late submission. Assessment Schedule (When): Semester 2, Approx. Week 5 | 0 | 15 | ||||
Assessment 1 Resit opportunity for this component is available via another coursework. Standard UoL penalty applies for late submission. Assessment Schedule (When): Semester 1, Approx. Week 11 | 0 | 10 |
Reading List |
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Reading lists are managed at readinglists.liverpool.ac.uk. Click here to access the reading lists for this module. |