Module Specification

The information contained in this module specification was correct at the time of publication but may be subject to change, either during the session because of unforeseen circumstances, or following review of the module at the end of the session. Queries about the module should be directed to the member of staff with responsibility for the module.
Title Digital Electronics & Microprocessor Systems
Code ELEC211
Coordinator Dr V Selis
Electrical Engineering and Electronics
V.Selis@liverpool.ac.uk
Year CATS Level Semester CATS Value
Session 2021-22 Level 5 FHEQ Second Semester 15

Aims

To provide students with the ability to: Understand and work with basic components of combinational digital circuits. Use and understand advanced techniques for logic minimisation. Understand memory and sequential logic, and how to develop circuit designs which incorporate them. Understand synchronous circuits and how to develop them. Analyse and design digital systems using the Algorithmic State Machine (ASM) methodology. Begin to contextualise ASMs within a top-down design methodology. Understand the features of Programmable Logic Devices (PLDs) and use them in their designs, including programming a field-programmable gate array (FPGA) with suitable techniques such as the use of a HDL. Interface memory and other peripherals to microprocessor systems. Provide knowledge of microprocessor systems with a good understanding of how basic microprocessors work. Understand basic assembly language programs. Know the different data formats such as ASCII, 2's complement and floating poin t format and more advanced microprocessor concepts such as pipelines and Harvard architecture.


Pre-requisites before taking this module (other modules and/or general educational/academic requirements):

ELEC143 Digital & Integrated Electronics Design 

Co-requisite modules:

 

Learning Outcomes

(LO1) Demonstrate a knowledge of digital electronics including combinational and sequential logic, algorithmic state machine (ASM) design techniques, Quine-McCluskey method and Karnuagh map-entered variables.

(LO2) Demonstrate an ability to design digital electronics using FPGA and a hardware description language.

(LO3) Demonstrate a knowledge of microprocessor concepts including architecture, assembly language, standard formats for negative and floating point numbers.

(LO4) Demonstrate a knowledge of more advanced microprocessor concepts including von Neuman/ Harvard architectures, pipelining and memory cache.

(LO5) Demonstrate an ability to understand assembly language code and use assembly language to write simple computer programs on a basic microprocessor.

(S1) Information technology (application of) adopting, adapting and using digital devices, applications and services

(S2) Numeracy (application of) manipulation of numbers, general mathematical awareness and its application in practical contexts (e.g. measuring, weighing, estimating and applying formulae)

(S3) Problem solving/ critical thinking/ creativity analysing facts and situations and applying creative thinking to develop appropriate solutions.


Syllabus

 

DIGITAL ELECTRONICS:  
Revision of Boolean logic, basic gates, functions, truth tables and Karnaugh maps. Minterms, maxterms, minimum and canonical sum of products (SOP). Multiplexers, decoders, tristate gates, programmable logic arrays (PLA), programmable array logic (PAL) and read-only memory (ROM). Shannon’s Expansion (applied to function decomposition), the Quine-McCluskey method and Map-Entered Variables (MEV).

Latches, flip-flops and registers. Complex programmable logic devices (CPLD) and field-programmable gate arrays (FPGA). Analysis of clocked sequential circuits; sequential and synchronous circuit design including revision and extension of timing diagrams, state transition tables and state graphs. Next-state and output maps. State machines (including Moore/Mealy), and Algorithmic State Machine (ASM) design, methods and pitfalls. Flip-flops for storing state variables; ‘one hot’ and ‘encoded’ state representations. Ser ial coding schemes and code conversion circuit design.

Design optimisation principles with n-bit adders including serial, parallel (ripple-carry) and carry look-ahead adders (CLA). Introduction to Verilog, Quartus II and schematic capture for design and simulation with a FPGA.

MICROPROCESSOR SYSTEMS:
Revision of binary, hexadecimal and ASCII.

Basic Microprocessor Organisation: CPU, ALU and memory. Data, address and control buses. Fetch, decode, execute cycles. Registers, basic instructions - moving data, mathematical and logical operations.

Assembly language programming: Mnemonics. Addressing modes. Program counter and branches. Conditional instructions and flags. Negative number representations. Use of the carry, overflow, negative and zero flags. Floating point numbers (IEEE 754 standard). The barrel shifter and shift instructions. Endianness, load and store instructions. Subroutines, link register, branch and link. Stacks and stack pointer. Interrupt s.

Advanced microprocessor architecture: Instruction pipelines. Von Neuman/Harvard architectures. Memory cache. Memory addressing. ARM processor modes. Exception handling.


Teaching and Learning Strategies

Due to Covid-19, one or more of the following delivery methods will be implemented based on the current local conditions and the situation of registered students.
(a) Hybrid delivery, with social distancing on Campus
Teaching Method 1 - On-line asynchronous lectures
Description: Lectures to explain the material
Attendance Recorded: No
Notes: On average two per week

Teaching Method 2 - Synchronous face to face tutorials
Description: Tutorials on the Assignments and Problem Sheets
Attendance Recorded: Yes
Notes: On average one per week

Teaching Method 3 - Laboratory Work
Description: Laboratory Sessions to undertake Experiments 26 & 28
Attendance Recorded: Yes
Notes: 1 day per Experiment

(b) Fully online delivery and assessment
Teaching Method 1 - On-line asynchronous lectures
Description: Lectures to explain the material
Attendance Re corded: No
Notes: On average two per week

Teaching Method 2 - On-line synchronous tutorials
Description: Tutorials on the Assignments and Problem Sheets
Attendance Recorded: Yes
Notes: On average one per week

Teaching Method 3 - on-line Laboratory Work Tutorials
Description: on-line laboratory Sessions to undertake Experiments 26 & 28 simulations
Attendance Recorded: Yes
Notes: 1 day per Experiment

(c) Standard on-campus delivery with minimal social distancing
Teaching Method 1 - Lecture
Description: Lectures to explain the material
Attendance Recorded: Yes
Notes: On average two per week

Teaching Method 2 - Tutorial
Description: Tutorials on the Assignments and Problem Sheets
Attendance Recorded: Yes
Notes: On average one per week

Teaching Method 3 - Laboratory Work
Description: Laboratory Sessions to under take Experiments 26 & 28
Attendance Recorded: Yes
Notes: 1 day per Experiment


Teaching Schedule

  Lectures Seminars Tutorials Lab Practicals Fieldwork Placement Other TOTAL
Study Hours 32

    14

  15

61
Timetable (if known)              
Private Study 89
TOTAL HOURS 150

Assessment

EXAM Duration Timing
(Semester)
% of
final
mark
Resit/resubmission
opportunity
Penalty for late
submission
Notes
(211) Formal written examination There is a resit opportunity. This is an anonymous assessment. Assessment Schedule (When) :Semester 2 examination period    75       
(211.3) Three 1-hour class tests, each worth 1/3 of the total ‘class test’ coursework mark. There is a resit opportunity. Non-standard penalty applies for late submission - Hard deadline. This is    10       
CONTINUOUS Duration Timing
(Semester)
% of
final
mark
Resit/resubmission
opportunity
Penalty for late
submission
Notes
(211.1) Experiment 28 Altera FPGA Assessment Schedule (When) :As scheduled    10       
(211.2) Experiment 26 ARM microprocessor Standard UoL penalty applies for late submission. This is an anonymous assessment. Assessment Schedule (When) :As scheduled         

Reading List

Reading lists are managed at readinglists.liverpool.ac.uk. Click here to access the reading lists for this module.