Module Specification |
The information contained in this module specification was correct at the time of publication but may be subject to change, either during the session because of unforeseen circumstances, or following review of the module at the end of the session. Queries about the module should be directed to the member of staff with responsibility for the module. |
Title | ADVANCED EMBEDDED SYSTEMS | ||
Code | ELEC470 | ||
Coordinator |
Dr S Khursheed Electrical Engineering and Electronics S.Khursheed@liverpool.ac.uk |
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Year | CATS Level | Semester | CATS Value |
Session 2020-21 | Level 7 FHEQ | Whole Session | 15 |
Aims |
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This module covers material for understanding and designingadvanced embedded computer systems. Key topics include computer architecture, low-powerdesign, hardware/software co-design and logic synthesis techniques. |
Pre-requisites before taking this module (other modules and/or general educational/academic requirements): |
Co-requisite modules: |
Learning Outcomes |
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(LO1) Students will achieve a full understanding of modernembedded systems including computer architecture, low-power design, hardware/softwareco-design and logic synthesis techniques. |
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(LO2) On successful completion the student should be able to understand published data concerning use of typical computer system design and components. |
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(S1) On successful completion of the module, students should be able to show experience and enhancement of the following key skills: Independent learning, Problem solving and design skills. |
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(S2) On successful completetion the student should be able to understand published literature on topics related to low-power embedded systems. |
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(S3) After scuccessful completion of the module, the student should have: an understanding of the internal operation of CPU, computer architecture, low-power design techniques, hardward/software co-design and logic synthesis techniques. |
Syllabus |
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Characteristics of E mbedded Systems Computer Architecture ALU architecture Memory cache Low power digital circuit design Synthesis of digital systems Hardware/Software Co-design |
Teaching and Learning Strategies |
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Due to Covid-19, one or more of the following delivery methods will be implemented based on the current local conditions and the situation of registered students. It is anticipated that both a) & b) will be in operation for semester 1. Teaching Method 2 - Synchronous face to face tutorials (b) Fully online delivery and assessment Teaching Method 2 - On-line synchronous tutorials (c) Standard on-campus delivery with minimal social distancing Teaching Method 2 - Tutorial |
Teaching Schedule |
Lectures | Seminars | Tutorials | Lab Practicals | Fieldwork Placement | Other | TOTAL | |
Study Hours |
24 |
12 13 |
49 | ||||
Timetable (if known) | |||||||
Private Study | 101 | ||||||
TOTAL HOURS | 150 |
Assessment |
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EXAM | Duration | Timing (Semester) |
% of final mark |
Resit/resubmission opportunity |
Penalty for late submission |
Notes |
Exam There is a resit opportunity. Standard UoL penalty applies for late submission. Assessment Schedule (When) :Semester 2 examination period | 3 hours | 75 | ||||
CONTINUOUS | Duration | Timing (Semester) |
% of final mark |
Resit/resubmission opportunity |
Penalty for late submission |
Notes |
SystemC Lab There is a resit opportunity. Standard UoL penalty applies for late submission. Assessment Schedule (When) :During semester 2 | 3 hours | 6 | ||||
coursework There is a resit opportunity. Standard UoL penalty applies for late submission. Assessment Schedule (When) :During semester 2 | 9 hours self-study | 19 |
Reading List |
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Reading lists are managed at readinglists.liverpool.ac.uk. Click here to access the reading lists for this module. |